Here is another FIFO Depth calculation. The write side is 5MHz 10 bits and read side is 4MHz 12 bits. What is the minimum depth required for continuous data transfer.
Fifo design
FIFO Design #1
Here is a FIFO design challenge.
I want to design an asynchronous FIFO. The write clock frequency is 100.1 MHz and read clock frequency is 100.9 MHz. What is the minimum depth required for an uninterrupted data transfer ?
Also what will be the depth required if the frequencies are interchanged ?
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